1. Technical Field
The present invention relates generally to an improved data processing system and method. In particular, the present invention provides a system and method for executing fixed point divide operations using a floating point multiply-add pipeline.
2. Description of Related Art
High performance computations in modern processors can be achieved through a number of architectural features. One such feature is the pipelined floating point execution units which allow several operations to take place in parallel. For example, fused floating-point multiply-add instructions allow two basic floating-point operations to be performed with a single rounding error.
To increase the speed and efficiency of real-number computations, floating point execution units in typical computers represent real numbers in a binary floating point format. In this format, a real number has three parts, a sign, a mantissa, and an exponent. The sign is a binary value that identifies whether the number is positive or negative. The mantissa is the numeric value which is multiplied by a base or radix raised to the power of the exponent, e.g., the mantissa of 145,000 is 145 (145×10^3). The mantissa is represented as a one bit binary integer and a binary fraction. The one bit binary integer is often not represented but is instead an implied value. The exponent is a binary integer that represents the base-2 power that the mantissa is raised to.
In most cases, the floating point execution unit represents real numbers in normalized form. This means that, except for zero, the mantissa is always made up of an integer of 1 and the fraction 1.fff . . . ff. For example, the normalized mantissa of the single precision representation for the ordinary decimal number 178.125 is represented by the floating point execution unit as 01100100010000000000000 (with the “1.” implied). For values less than 1, leading zeros are eliminated. For each leading zero that is eliminated, the exponent is decremented by one, resulting in an exponent with a negative value.
The floating point execution unit represents exponents in a biased form. This means that a constant is added to the actual exponent so that the biased exponent is always a positive number or zero, even when its value is negative. The value of the biasing constant depends on the number of bits available for representing exponents in the floating point format being used, which depends upon which precision is used. The biasing constant is chosen so that the smallest normalized number can be reciprocated without overflow. In the above example, the biased single precision exponent for the decimal number 178.125 is represented as 10000110. Thus, in scientific notation, the number 178.125 is the combination of the normalized mantissa and the biased exponent, i.e. 1.011001000E210000110.
While the floating point execution unit is used to execute floating point instructions, modern computers make use of fixed point units for executing fixed point or integer based instructions. In most modern processors, for example, fixed point divide instructions, also referred to as integer divide instructions, are usually implemented using a specialized custom design sub-unit within a fixed point unit. This specialized sub-unit requires additional area and power for the processor architecture. Frequently, these designs also have very long latency for large operands, such as for 64 bit operands, in order to keep the additional area small.
It would be beneficial to have a hardware based mechanism for executing fixed point divide instructions in such a way that the high performance obtained from floating point execution units may also be achievable when executing fixed point divide instructions. In addition, it would be beneficial to have a hardware based mechanism for executing fixed point divide instructions that reduces the required amount of area and power for the processor architecture.